%Huichu's section
\subsection{Variation in steep-slope multicores}
In addition to the noise challenge discussed above, steep-slope devices are also prone to process variations due to their operation at reduced supply voltage and the steep transition of their current characteristics.
For III-V HTFET, variation sources that can alter the tunneling barrier width can cause a significant $I_{on}$ fluctuation given the exponential current dependence on the tunneling barrier width~\cite{VinayNanoarch2011, AvciIEDM2013}. 
Variation sources such as fluctuations in source doping, oxide thickness, gate-contact work function, left/right gate edge overlap, body thickness have been investigated from the device to circuit level~\cite{VinayNanoarch2011}, among which the work function variation dominates, considering the reported process data~\cite{AvciIEDM2013}. Fig.~\ref{fig:device-variation} shows the transistor delay fluctuation corresponding to the threshold voltage shift caused by the gate work function variation, based on the Verilog-A models of $L_g$=20 nm HTFET and Si FinFET. HTFET exhibits an overall lower delay variation compared to Si FinFET for $V_{dd} < 0.5V$ while Si FinFET operates in the near- or sub- threshold region. 

\begin{figure}[ht!]
\centering
%\epsfig{file=figs/modeling.eps, angle=0, height=0.6\linewidth, clip=}
\epsfig{file=figs/device_variation.eps, angle=0, width=0.9\linewidth, clip=}
\caption{\label{fig:device-variation} Impact of effective $V_{th}$ shift on transistor switching delay for a) TFETs and b) Si FinFETs. The effective $V_{th}$ shift in TFET is a reflection of the gate-contact work function variation. }
\end{figure}

\subsection{ Observing device variations at the architecture level}
Based on the different sources of variations at the device level, we classify the variations as global (constant) and random variations.
As observed, the variation in work function, an inherent atomistic property of transistors, dominates the overall variation for TFETs~\cite{AvciIEDM2013}.
In a similar manner, the corresponding variation in FinFETs can be modeled as a zero mean Gaussian with a work function variation of around 50~mV, as demonstrated in~\cite{seoane-workfunction}.
The remaining sources of variation, allied with variation components localized to a section of the wafer, can be assumed to encompass 3-5\% of the total variation~\cite{kuhn-variation}.

In order to model the critical path of a processor, we assume a number of such variation-affected transistors cascaded together. In order to determine the exact length of this critical path, we carry out a critical path analysis using \emph{Fabscalar}~\cite{fabscalar}. This tool generates synthesizable HDL code for different micro-architectural configurations, by varying parameters such as the issue width, pipeline depth and number of execution units. 
Further details regarding the standard cell libraries used for synthesizing TFET processor model are given in~\cite{karthik-date14}.

Figures~\ref{fig:variation-arch-volt}~and~\ref{fig:variation-arch-freq} show the dependence on the worst case (3$\sigma$) variation in delay on supply voltage and frequency respectively, for both FinFET and TFET-based processors. The processor model used was a 4-issue Ivybridge configuration with logic and wire models obtaine using techniques similar to those in~\cite{karthik-isca}.
These figures lead us to draw the following conclusions. Firstly, TFET processors are less susceptible to variations at low $V_{dd}$ than their FinFET counterparts. Also, the variation behavior in the region of optimal operation of both core types are roughly similar (within $\pm$ 10\% of each other).

\begin{figure}[ht!]
\begin{minipage}[b]{0.48\linewidth}
  \centering
    \epsfig{file=figs/variation_voltage.eps, angle=0, width=1.02\linewidth, clip=}
    \caption{\footnotesize\label{fig:variation-arch-volt} Dependence of variation on supply voltage}
\end{minipage}
%\end{figure}
\hspace{0.2in}
%%\begin{figure}[ht!]
\begin{minipage}[b]{0.48\linewidth}
  \centering
    \epsfig{file=figs/variation_frequency.eps, angle=0, width=1.02\linewidth, clip=}
    \caption{\footnotesize\label{fig:variation-arch-freq} Dependence of variation on frequency }
\end{minipage}
\end{figure}

\subsection{Variation mitigation using voltage scaling}
In order for a system to meet its specified performance criterion in the presence of variation, it is possible to boost the supply voltage to compensate for the additional worst-case variation-induced delay. Doing so, however, comes at the cost of additional dynamic and leakage power. 
As shown in Figure~\ref{fig:variation-arch-volt}, both the distribution of variation and its worst case ($\mu \pm 3\sigma$), depend on the target supply voltage.
Further, in case of TFET processors, this can also shift the effective crossover point, i.e $f_c$, below which TFET cores are more power efficient than CMOS cores.
Since the variation of TFETs becomes higher than CMOS for supply voltages above $V_t$, the crossover point, which falls in this super-threshold region is shifted to the left due to the additional voltage boost required by TFETs to compensate for the increase in worst-case delay.
Figure~\ref{fig:crossover-variation} shows the effect of these overall variations on the TFET-CMOS crossover plot.

\begin{figure}[ht!]
  \centering
    \epsfig{file=figs/crossover_variation.eps, angle=0, width=1\linewidth, clip=}
    \caption{\footnotesize\label{fig:crossover-variation} Power-frequency curves for CMOS and TFET processors with and without the effects of variation. }
\end{figure}
